Standard Libraries in VHDL

VHDL designers are forced to include some standard libraries for compiling their design. It's similar to header files in programming languages. However, in Verilog HDL, you don't have the concept of libraries. This means that you could use operators like +, *, >,< directly in your Verilog code. 

Some libraries are IEEE recognised standard libraries, but some are built by EDA tool vendors like Synopsys. To make life harder for hardware designers, arithmetic operators and conversion functions are defined differently for each libraries, creating a conflict. 

As an example,  '+' operator is defined in both arith and unsigned libraries. But if you include both of them, your compiler pops-up an error. 

I would recommend to use the following IEEE libraries in your VHDL code : 

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

use ieee.numeric_std.all;

Additionally, to read/write from a file, you will need to include use std.textio.all to perform such functions. 

VHDL Type conversion function

Hello everyone,

In my undergraduate studies, I learnt Verilog before VHDL and hence I prefer to design in Verilog. In Verilog, there are just two data types for design, namely wire and reg. However, in VHDL, a signal / variable can be of different types like integer, std_logic, unsigned, signed etc. All these data types are used in different situation, eg:  '+'  operator is commonly used with unsigned data type.

For Verilog users who are migrating to VHDL, this becomes confusing to remember all the conversion functions. I found a figure which clearly shows all the conversion functions.

Answer record from Xilinx provides an example design of some conversion functions. 

AR# 45213