ARM gives away Digilent Nexys4 FPGA board !!!

ARM provides Digilent Nexys4 board as a part of the ARM University program. I got this board when I attended the Xilinx University Program workshop conducted by ARM and Xilinx at FCCM conference, Boston. Moreover, they provide a license (Verilog IP) for ARM-Cortex-M0 microcontroller which is commercially sold by ARM. The workshop was very interesting as it introduced the new Vivado design tools from Xilinx and integration with Keil IDE to develop software's for ARM processor. 

It was mentioned in the workshop that ARM is willing to provide these kits for Universities, free of charge, if it's used for teaching/research purposes. I feel this is a great opportunity for university professors and researchers to introduce ARM,SoC's and latest FPGA's in the university. Check the following link to request for a donation of FPGA boards/ SoC training materials from ARM :

Click here to go to ARM University program

FSL connection between a Custom IP with a processor in Xilinx FPGA

Custom IP is usually attached to processor to accelerate certain tasks/functions which are bottlenecks in the software. This post describes how to connect a custom IP with a microblaze soft processor in Xilinx FPGA.

As usual, Xilinx provides documentation for connecting custom IP with microblaze processor. This link is available here:

FSL documentation from Xilinx

Unfortunately for Xilinx FPGA designers, this document was published in 2004 and works with obsolete technologies which include On-chip Peripheral bus etc. Currently, all the latest Xilinx FPGA are AXI based which are a part of the AMBA bus protocol. Hence, this post outlines the procedures to add a custom IP and describes how to write software for an application.

Procedures:

1. After creating the microblaze design from BSB, double click microblaze to add an FSL port to the processor. In the tab Buses, add one AXI based FSL streaming interface to XPS.
2. To create a custom IP, go to Hardware-> Create or Import Custom IP option and create a custom IP to XPS. Make sure you select the FSL interface. You may choose the input/output register according to your application.
3. An HDL example code is generated in the pcores directory of the project. This HDL code can be modified depending on your application. In my application, I used one master interface of the FSL protocol. The slave interfaces and signals were undriven in my HDL code.
4. After making suitable modifications to VHDL design, import the modified core by going to Hardware-> Create or Import Custom IP option. Make sure to give the updated HDL source code to the tool and select the correct bus interface.
5. Make the FSL connection between microblaze and custom IP ie. slave connects to master and master connects to slave. This can also be done using the Configure co-processor option in EDK.
6. If control signal is not used in the design, double click the generated FSL bus IP and remove the propagate control bit option. Also in the ports section, make sure you connect FSL_CLK to CLKOUT0 from clock generator
7. Export design to SDK to write software and communicate with IP using blocking read/write functions supported by Xilinx. Please refer the following documentation  for available functions supported by  microblaze processor.

FSL documentation from Xilinx

Good Luck!!!

Standard Libraries in VHDL

VHDL designers are forced to include some standard libraries for compiling their design. It's similar to header files in programming languages. However, in Verilog HDL, you don't have the concept of libraries. This means that you could use operators like +, *, >,< directly in your Verilog code. 

Some libraries are IEEE recognised standard libraries, but some are built by EDA tool vendors like Synopsys. To make life harder for hardware designers, arithmetic operators and conversion functions are defined differently for each libraries, creating a conflict. 

As an example,  '+' operator is defined in both arith and unsigned libraries. But if you include both of them, your compiler pops-up an error. 

I would recommend to use the following IEEE libraries in your VHDL code : 

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

use ieee.numeric_std.all;

Additionally, to read/write from a file, you will need to include use std.textio.all to perform such functions. 

VHDL Type conversion function

Hello everyone,

In my undergraduate studies, I learnt Verilog before VHDL and hence I prefer to design in Verilog. In Verilog, there are just two data types for design, namely wire and reg. However, in VHDL, a signal / variable can be of different types like integer, std_logic, unsigned, signed etc. All these data types are used in different situation, eg:  '+'  operator is commonly used with unsigned data type.

For Verilog users who are migrating to VHDL, this becomes confusing to remember all the conversion functions. I found a figure which clearly shows all the conversion functions.

Answer record from Xilinx provides an example design of some conversion functions. 

AR# 45213

Creating a custom IP and integrating to Microblaze

Hi,

FPGA is used for various applications which involves complex processing and control of other devices. Typically, FPGA logic resources are used to do complex processing (using Verilog/VHDL hardware description languages) whereas a soft-processor like Microblaze is used to control other devices.

The following link is very useful which gives hands-on lab experience with emphasis on concepts and their implementation in EDK.

Xilinx Document :

Chapter 6 explains how to create a custom IP and integrate it with EDK.

As a continuation of this Xilinx tutorial, I would like to explain how to access custom IP from a C code.

Xilinx provides Xil_Out8 API to write to a particular address in EDK design.

Definition of function is as follows:

void Xil_Out8(uint32 address=,uint8 data);

Eg: Xil_Out8(2019557376=,255);

Note: Do not forget to include #include "xil_io.h" to use these API's.

The following link has information of all other API from Xilinx.

OS and Libraries Document Collection

Writing/Reading data from Compact flash from FPGA

Do you know how to read/write from Compact flash from an FPGA board ?

Last week, I was trying to do read/write operations to compact flash using FPGA. As usual, it was very difficult to get good documentation to do this.

A summary of the procedure to access files in a Xilinx FPGA board(ML605) is as follows: 

1. Created an XPS project (Microblaze based) and added compact flash IP to the design 

2. Generated bitstream and exported the design to SDK

3. Created a new software project - added the Libxil FAT system library in MSS project settings

4. Wrote a C code to open a file, read/write file ( by reading LibXil documentation)

5. Increase the stack and heap size of the application (to allow dynamic memory allocation) and store application in DDR memory by generating linker script. 

Note : There is no change in jumper settings (for ML605) and default files in compact flash are not to be modified. 

Check out the following links for more details:

http://forums.xilinx.com/t5/Embedded-Development-Tools/Write-1M-data-to-Compact-Flash/td-p/433398

http://www.dte.us.es/share/sde/Cursos_IMEC-XUP_1.6/Lab16V1.1_%20Software%20implementation%20of%20an%20MP3%20player%20%28EDK%208.2%29/Lab16Mod2V1.0.pdf