FSL connection between a Custom IP with a processor in Xilinx FPGA

Custom IP is usually attached to processor to accelerate certain tasks/functions which are bottlenecks in the software. This post describes how to connect a custom IP with a microblaze soft processor in Xilinx FPGA.

As usual, Xilinx provides documentation for connecting custom IP with microblaze processor. This link is available here:

FSL documentation from Xilinx

Unfortunately for Xilinx FPGA designers, this document was published in 2004 and works with obsolete technologies which include On-chip Peripheral bus etc. Currently, all the latest Xilinx FPGA are AXI based which are a part of the AMBA bus protocol. Hence, this post outlines the procedures to add a custom IP and describes how to write software for an application.

Procedures:

1. After creating the microblaze design from BSB, double click microblaze to add an FSL port to the processor. In the tab Buses, add one AXI based FSL streaming interface to XPS.
2. To create a custom IP, go to Hardware-> Create or Import Custom IP option and create a custom IP to XPS. Make sure you select the FSL interface. You may choose the input/output register according to your application.
3. An HDL example code is generated in the pcores directory of the project. This HDL code can be modified depending on your application. In my application, I used one master interface of the FSL protocol. The slave interfaces and signals were undriven in my HDL code.
4. After making suitable modifications to VHDL design, import the modified core by going to Hardware-> Create or Import Custom IP option. Make sure to give the updated HDL source code to the tool and select the correct bus interface.
5. Make the FSL connection between microblaze and custom IP ie. slave connects to master and master connects to slave. This can also be done using the Configure co-processor option in EDK.
6. If control signal is not used in the design, double click the generated FSL bus IP and remove the propagate control bit option. Also in the ports section, make sure you connect FSL_CLK to CLKOUT0 from clock generator
7. Export design to SDK to write software and communicate with IP using blocking read/write functions supported by Xilinx. Please refer the following documentation  for available functions supported by  microblaze processor.

FSL documentation from Xilinx

Good Luck!!!