Standard Libraries in VHDL

VHDL designers are forced to include some standard libraries for compiling their design. It's similar to header files in programming languages. However, in Verilog HDL, you don't have the concept of libraries. This means that you could use operators like +, *, >,< directly in your Verilog code. 

Some libraries are IEEE recognised standard libraries, but some are built by EDA tool vendors like Synopsys. To make life harder for hardware designers, arithmetic operators and conversion functions are defined differently for each libraries, creating a conflict. 

As an example,  '+' operator is defined in both arith and unsigned libraries. But if you include both of them, your compiler pops-up an error. 

I would recommend to use the following IEEE libraries in your VHDL code : 

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

use ieee.numeric_std.all;

Additionally, to read/write from a file, you will need to include use std.textio.all to perform such functions.